// php echo do_shortcode (‘[responsivevoice_button voice=”US English Male” buttontext=”Listen to Post”]’)?>
Lam Research Corporation’s latest suite of selective etch products are designed to help chipmakers leap from planar to 3D structures for DRAM as it reaches its planar scaling limit. Thomas Bondur, the company’s etch business unit corporate vice president for product marketing and business development, explained this is part of a broader trend toward developing transistor structures vertically to keep pace with Moore’s law.
As chipmakers continue to accelerate their 3D roadmaps, tooling vendors aren’t just tasked with keeping pace with today’s needs but also readying their offerings to anticipate future requirements. Building up is an exceptionally complex process that requires ultra – high selectivity, Bondur said.
Lam’s new suite of selective etch products, Argos, Prevos, and Selis, support chipmakers in the development of gate-all-around (GAA) transistor structures through novel wafer fabrication techniques and chemistries. The products also allow for ultra – high selectivity, precision etching, and uniform isotropic removal of material without modifying or causing damage to other critical material layers.
Damage – free material removal is becoming more critical as chipmakers work with vertical structures because isotropic etch is required in more steps to define critical device features, Bondur said. In addition, the surrounding material is chemically similar to the targeted material being removed, which means high selectivity must be maintained even though the material contrast is very low.
“Encapsulating materials meant to protect critical features are getting thinner and with reduced etch resistance,” Bondur said. “Both high selectivity and Angstrom – precision over etch control are required to avoid damage from leakage paths through the encapsulating material.”
Even interfaces between the target material and underlying / surrounding material must be either selectively removed or kept in place, Bondur said. Therefore, high selectivity must be maintained even though there is virtually no material contrast. Essentially, the incoming material is more heterogeneous and is driving the requirements for precision damage – free removal.
Each of Lam’s etch products play a role in addressing the challenges of developing transistor structures vertically. Used for selective surface treatment, Argos employs the company’s metastable active radical source technology create to what Bondur said is the world’s gentlest radical plasma, which is necessary for highly selective surface property modification needed in advanced logic applications.
Prevos is comprised of a proprietary chemistry catalyst developed specifically for the extremely high selectivity requirements of applications, such as native oxide breakthrough, precision trim, and recess, he said.
Selis offers low energy processing mode designed for the most extreme applications where selectivity must be ultra – high, such as with the critical SiGe selective etch steps used to form GAA structures. “The process is so well controlled that Selis can etch SiGe layers without damaging or roughening the critical Si layers.”
Bondur explained all devices drive the need for ultra – high selectivity, zero damage, ultra – low material losses, and uniform top – to – bottom control. “Lateral etch profile is key to performance for all devices.”
Specific structures that are driving the needs for precision selective etch include logic GAA structures beginning at around 3nm nodes and future 3D DRAM and 3D NAND devices, which will also be vertical stacked devices with numerous requirements for precision selective etch technology, according to Bondur.
While NAND was the pioneer in 3D stacking, Lam is seeing logic scaling transistor structures transitioning to 3D with DRAM to follow. Bondur said the company is already well established with its Selis selective etch product in logic FinFET and are now seeing growing interest with the recent move toward production for logic GAA devices.
“For 3D DRAM, we have already begun the development work on these structures,” Bondur said. He also explained Lam products are designed for whole wafer handling solutions, but the company could add a design modification for a chiplet handling approach depending on future market requirements.
– Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.
ALD Technology Fills Taller Memory
IMW Highlights 3D Architectures, In-Memory Computing
Micron Leapfrogs to 176-Layer 3D NAND Flash Memory